A computer platform with a set-associative cache may experience contention among multiple software components executing on the platform when more than one block of RAM (random access memory) is assigned to a common set of the cache. For example, the hardware of the computer platform may specify that hundreds or thousands of RAM blocks be serially assigned to each cache set, the assignment circling over the cache many times until each block of RAM is assigned. Because RAM is typically allocated to a variety of software components without referencing the RAM/CACHE mapping, contention may result, causing unpredictable performance for a software component such as an application, a task, or a thread. One solution to hardware-caused contention is to increase the number of lines in each set of the cache, each line being capable of holding a block of code or data attempting to utilize that set of cache. However, each set of the cache may still be assigned to multiple blocks of RAM. In particular, some computer platforms, such as integrated modular avionics (IMA) architectures, may have software components that need to operate deterministically and for which contention is a larger problem.
One possible solution to cache contention is to develop custom computer hardware which allows a user to set aside a spatial partition in the cache where a particular software component situated in RAM may be assigned its own region of cache. However, a hardware solution may be prohibitively expensive, particularly for a product having a low volume in the commercial marketplace. Another solution is to allocate a CPU core to one or more software components for which deterministic performance is desired. However, other computer resources, such as one or more caches, may still be shared and cause contention. Still another solution to contention is time multiplexing of the cache among software components. Unfortunately, periodically setting up and tearing down the time partition may slow execution time for a critical software component.